Does the offer of a full undiced wafer drive away commercial customers who don’t want someone else getting hands on their bare dice, or is everything on wafer.space submissions initially expected to be open source?
Not sure if it's applicable in this case, but it's possible to mask out some designs from a water by making an extra mask that blocks out specific parts of the reticle
I brought up that issue as well. I doubt anyone would actually use this vector to obtain anyone else's designs or IP, but at the end of the day it's kinda selling someone else's stuff.
@urish there's also the possibility of just destroying the ones that are not yours after the fact. Drill a hole, use a laser to just ruin it a little.
algofoogle (Anton Maurovic)
Does the offer of a full undiced wafer drive away commercial customers who don’t want someone else getting hands on their bare dice, or is everything on wafer.space submissions initially expected to be open source?
"Custom silicon. Manufactured."
This does not give customers a good reason to go with wafer.space over any other fab option. They all do "custom silicon" and manufacture it.
It's a question for Tim. What makes wafer.space different?
IMHO no NDA is a big deal.
Open source PDK is another one.
Cost and number of parts you get is a third.

MOSbius, developed by Professor Peter Kinget and his students at Columbia University, is an innovative educational platform that helps students and designers explore MOS circuit topologies typically found on silicon and now accessible on a breadboard.
The goal of MOSbius is to give learners hands-on experience with transistor-level design, including circuit debugging, measurement, and the full “chip bring-up” process. The platform allows users to compare calculations, simulations, and real measurements using provided LTspice models, bridging the gap between theory and silicon.
MOSbius – A Field Programmable Transistor Array for Chip DesignersInterview with Peter Kinget
Their current board design requires numerous passive components due to varying pin voltage levels, and each packaged chip can cost upwards of $50. With their new design on the Wafer.Space platform, all pins will be 3.3 V tolerant, dramatically simplifying their demo board and lowering overall complexity.
By leveraging Wafer.Space’s low-cost fabrication process, the MOSbius team is able to minimize production expenses and make their chips available to the educational community at a nominal cost — expanding access to hands-on silicon learning for students and researchers worldwide.
We’re thrilled to have MOSbius as part of this shuttle run and proud to support a project that aligns so perfectly with Wafer.Space’s mission!
Learn more about the project at mosbius.org.
Given the unique requirements of the MOSbius project, the team is designing their own version of a Chip-on-Board (COB) package based on the Wafer.Space standard padframe.
Their application prioritizes a high number of I/O connections over power and ground pads, allowing for the maximum number of accessible signals from their transistor array.
Peter’s student, @xianglin_pui, has taken the lead on this effort and developed derivative designs that extend the Wafer.Space COB standard for MOSbius’s specialized needs.
12:39 p.m.
@peterkinget I would like to post this in one of the upcomming updates. Would you like to add anything or make any changes?
Thanks!